Engineer / Senior Engineer – Physical Verification & Parasitic Extraction

About the role

The Engineer / Senior Engineer will join SilTerra’s Design Enablement – CAD team to develop and maintain physical verification runsets and parasitic extraction rule sets across a range of semiconductor technologies. The role focuses on ensuring design rule compliance and accurate extraction for core, IoT, high‑voltage, BCD, MEMS and silicon photonics products.

Key responsibilities

• Develop and maintain DRC and LVS runsets for multiple technology nodes.
• Create and update parasitic extraction rule sets such as PEX, ITF, NXTGRD, ICT and QRC.
• Design test structures to validate runsets and rule sets before customer release.
• Build and use automation tools to streamline development and validation workflows.
• Provide prompt technical support for customer issues related to verification and extraction.

Required profile

• Proven experience in developing and maintaining physical verification and parasitic extraction rule sets.
• Familiarity with semiconductor technology domains including core, IoT, HV, BCD, MEMS and silicon photonics.
• Ability to create test structures and automate validation processes.
• Strong problem‑solving skills and customer‑focused attitude.

Required skills

• DRC (Design Rule Check)
• LVS (Layout Versus Schematic)
• Parasitic extraction tools (PEX, ITF, NXTGRD, ICT, QRC)
• Automation scripting or tool development